Many layers of connectivity are required in typical backend processing for semiconductor chips such as for cell and plate fabrication of dynamic random-access memory cells. Several techniques have been used including forming a plate metal layer that is used to connect to the tops of individual capacitors. This requires an extra metal layer, complete with the usual lithography requirements, etch requirements, capacitor cell-filling requirements, and polishing associated with dual-damascene processing. Another method is to separately pattern a plate connection directly on top of the capacitor cell, which also requires several processes.